Process
A concurrent statement which describes behaviour. A process is itself a
concurrent statement, but it contains sequential statements that execute in
series from top to bottom. A process executes at times controlled by the
sensitivity list or by wait statements.
Syntax
[Label:] [postponed] process [ (SensitivityList) ] [is]
Declarations...
begin
SequentialStatements...
end [postponed] process [Label];
SensitivityList = SignalName, ...
Where
entity-begin--end {passive process}
architecture-begin--end
block-begin--end
generate-begin--end
Rules
A process must contain either a sensitivity list or wait statements, but not
both.
Every process executes once during initialization, before simulation starts.
A postponed process is not executed until the final simulation cycle of a
particular simulation time, and thus sees the stable values of signals and
variables.
Things to remember
A process with neither a sensitivity list nor a wait will loop forever.
Synthesis
Processes are one of the most useful VHDL statements for synthesis, yet
many processes are unsynthesizable. For best results, code should be
restricted to the following process templates:
process (Inputs) -- All inputs in sensitivity list
begin
... -- Outputs assigned for all input conditions
... -- No feedback
end process; -- Gives pure combinational logic
process (Inputs) -- All inputs in sensitivity list
begin
if Enable = '1' then
... -- Latched actions
end if;
end process; -- Gives transparent latches + logic
process (Clock) -- Clock only in sensitivity list
begin
if Rising_edge(Clock) then -- Test clock edge only
... -- Synchronous actions
end if;
end process; -- Gives flipflops + logic
process (Clock, Reset) -- Clock and reset only in sensitivity list
begin
if Reset = '0' then -- Test active level of asynchronous reset
... -- Asynchronous actions
elsif Rising_edge(Clock) then -- Test clock edge only
... -- Synchronous actions
end if;
end process; -- Gives flipflops + logic
process -- No sensitivity list
begin
wait until Rising_edge(Clock);
... -- Synchronous actions
end process; -- Gives flipflops + logic
Example
The following example shows a Register Transfer Level process:
Counter: process (Reset, Clock)
begin
if Reset = '0' then -- Asynchronous reset
Count <= (others => '0');
elsif Rising_edge(Clock) then
if Load = '0' then -- Synchronous load
Count <= Data;
else
Count <= Count + '1';
end if;
end if;
end process Counter;
The following example shows processes used to generate vectors in a test
bench:
signal StopClock: Boolean;
signal Clk: Std_logic;
constant Period: Time := 10 NS;
subtype Int8 is Std_logic_vector(7 downto 0);
signal A, B: Int8;
type Operation is (Load, Store, Move, Halt);
signal Op: Operation;
...
ClockGenerator: process
begin
while not StopClock loop
Clk <= '0';
wait for Period/2;
Clk <= '1';
wait for Period/2;
end loop;
wait;
end process ClockGenerator;
Stimulus: process
type Table is array (Natural range <>) of Int8;
constant Lookup: Table :=
("00000000", "00000001", "00000011", "00001000",
"00001111", "10000000", "11111000", "11111111");
begin
for L in 1 to 2 loop
for I in Lookup'Range loop
B <= Lookup(I);
for J in Lookup'Range loop
A <= Lookup(J);
for K in Operation loop
Op <= K;
wait for Period;
end loop;
end loop;
end loop;
StopClock <= True; -- Flag to stop clock generator process
end loop;
wait;
end process Stimulus;
See Also
Concurrent Statement, Sequential Statement, Wait
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